1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit, to a layout method of a semiconductor integrated circuit, and to a layout apparatus of a semiconductor integrated circuit. More particularly, the present invention relates to a semiconductor integrated circuit, a layout method of the semiconductor integrated circuit, and a layout apparatus of the semiconductor integrated circuit, in which a second guard-ring is formed between respective input-output circuit portions.
This application is a counterpart of Japanese application Serial Number 301947/1997, filed Nov. 4, 1997, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
In general, in a conventional semiconductor integrated circuit having a CMOS circuit, there is a need to prevent latch-up. Latch-up occurs in a core portion that is made up of a main circuit of the semiconductor integrated circuit. Latch-up also occurs in an input-output circuit portion located between the core portion and an external portion of the semiconductor integrated circuit. Especially, latch-up occurs as a result of an external signal and a power supply noise in the input-output circuit portion.
A conventional input-output circuit portion is made up of a pad portion for a wire-bonding and a CMOS circuit. The conventional semiconductor integrated circuit can prevent latch-up using a well known guard-ring. The well known guard-ring has been disclosed in "VLSI SHISUTEMU SEKKEI-KAIRO TO JISSO NO KISO, KISABURO NAKAZAWA et al, Mar. 30, 1995, MARUZEN, pp. 54-56". The guard-ring is formed around transistors of the input-output circuit portions.
Concretely, a p+ guard-ring is electrically connected to a ground potential Vss line, which is formed around respective N-channel MOS transistors of the input-output circuit portions, and an n+ guard-ring is electrically connected to a power supply voltage VDD line, which is formed around respective P-channel MOS transistors of the input-output circuit portions. Further, the guard-ring is formed between the input-output circuit portion and the core portion. The guard-ring is used to decrease a resistivity of a well layer and a resistivity of a semiconductor substrate.